Memory device and method for driving same

ABSTRACT

A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromU.S. Provisional Patent Application 62/395,670, filed on Sep. 16, 2016;the entire contents of which are incorporated herein by reference.

FIELD

Embodiments relate to a memory device and a method for driving the same.

BACKGROUND

In recent years, there has been proposed a memory device in whichresistance change memory cells are integrated in three dimensions. Insuch a memory device, a resistance change film is provided between aword line and a bit line. Data are stored by controlling the resistancevalue of this resistance change film. Also in such a resistance changememory device, multivalued operation of memory cells is desired toincrease the memory density of data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view showing a memory device according to anembodiment;

FIG. 2 is a sectional view showing the memory device according to theembodiment;

FIG. 3A is a timing chart showing voltage applied to a resistance changefilm, while a horizontal axis representing time, and a vertical axisrepresenting voltage; FIG. 3B is a graph showing a behavior of a memorycell MC2, while a horizontal axis representing voltage applied to theresistance change film in a voltage application period, and a verticalaxis representing current flowing in the resistance change film in acurrent measurement period;

FIG. 4 is a graph showing a behavior of a memory cell MC1, while ahorizontal axis representing voltage, and a vertical axis representingcurrent; and

FIG. 5 is a timing chart showing an operation of the memory deviceaccording to the embodiment, while a horizontal axis representing time,and a vertical axis representing a potential applied to eachinterconnect.

DETAILED DESCRIPTION

A memory device according to an embodiment includes a first interconnectextending in a first direction, a second interconnect extending in asecond direction crossing the first direction, a third interconnectextending in a third direction crossing a plane including the firstdirection and the second direction, a fourth interconnect extending inthe third direction, a semiconductor member, a first resistance changefilm, and a second resistance change film. The semiconductor member isconnected between a first end of the second interconnect and the firstinterconnect. The first resistance change film is connected between aside surface of the second interconnect and the third interconnect. Thesecond resistance change film is connected between a second end of thesecond interconnect and the fourth interconnect.

Embodiments of the invention will now be described with reference to thedrawings.

FIG. 1 is a perspective view showing a memory device according to theembodiment.

FIG. 2 is a sectional view showing the memory device according to theembodiment.

As shown in FIGS. 1 and 2, the memory device 1 according to theembodiment includes a plurality of global bit lines 11. The global bitlines 11 are formed by partitioning an upper portion of a siliconsubstrate (not shown) by a device isolation insulator (not shown).Alternatively, the global bit lines 11 are formed by providing aninsulating film (not shown) on a silicon substrate and depositingpolysilicon thereon.

In the following, an XYZ orthogonal coordinate system is adopted in thespecification. The extending direction of the global bit lines 11 isreferred to as “X-direction”. The arranging direction of the global bitlines 11 is referred to as “Y-direction”. The direction orthogonal tothe X-direction and the Y-direction is referred to as “Z-direction”. Oneside of the Z-direction is also referred to as “upper”, and the other isalso referred to as “lower”. However, these expressions are used forconvenience, and irrelevant to the direction of gravity.

A plurality of silicon members 12 are provided on each global bit line11. As viewed in the Z-direction, the silicon members 12 are arranged ina matrix along the X-direction and the Y-direction. Each silicon member12 is shaped like a rectangular solid with the longitudinal direction inthe Z-direction. The lower ends 12 a of a plurality of silicon members12 arranged in a line along the X-direction are commonly connected toone global bit line 11.

Each silicon member 12 includes an n⁺-type portion 13, a p⁻-type portion14, and an n⁺-type portion 15 arranged in this order along theZ-direction from the lower side, i.e., from the global bit line 11 sidetoward the upper side. The relationship between the n-type and thep-type may be reversed.

Two gate electrodes 16 extending in the Y-direction are provided betweenthe silicon members 12 in the X-direction. The gate electrode 16 isformed from e.g. polysilicon. As viewed in the X-direction, the gateelectrode 16 overlaps an upper part of the n⁺-type portion 13, theentirety of the p⁻-type portion 14, and a lower part of the n⁺-typeportion 15.

A gate insulating film 17 made of e.g. silicon oxide is provided betweenthe silicon member 12 and the gate electrode 16. The silicon member 12including the n⁺-type portion 13, the p⁻-type portion 14, and then⁺-type portion 15, the gate insulating film 17, and a pair of gateelectrodes 16 sandwiching the silicon member 12 constitute a TFT 19 ofe.g. n-channel type. The TFT 19 is a switching element for switchingbetween conduction and interruption of current.

A local bit line 21 is provided on the silicon member 12. The local bitline 21 extends in the Z-direction. The local bit line 21 is shaped likee.g. a quadrangular prism. More specifically, the longitudinal directionof the local bit line 21 is the Z-direction. The length in theZ-direction of the local bit line 21 is longer than the length in theX-direction and the length in the Y-direction. The lower end 21 a andthe upper end 21 b of the local bit line 21 are both ends in theZ-direction of the local bit line 21.

The lower end 21 a of the local bit line 21 is connected to the upperend 12 b of the silicon member 12. Each local bit line 21 is placeddirectly above the corresponding silicon member 12. Thus, in the memorydevice 1 as a whole, a plurality of local bit lines 21 are arranged in amatrix along the X-direction and the Y-direction.

A resistance change film 22 is provided on both side surfaces 21 cfacing the X-direction of the local bit line 21. The resistance changefilm 22 is a film in which the resistance state is changed by thevoltage or current applied thereto. The resistance change film 22 ismade of e.g. metal oxide such as hafnium oxide (HfO₂). The resistancechange film 22 may be a CBRAM (conductive bridging random access memory)film or PCRAM (phase change random access memory) film.

A plurality of word lines 23 extending in the Y-direction are providedbetween the local bit lines 21 adjacent in the X-direction, and spacedfrom each other in the Z-direction. As viewed in the Y-direction, theword lines 23 are arranged in a matrix along the X-direction and theZ-direction. The resistance change film 22 is connected between thelocal bit line 21 and the word line 23. Thus, a memory cell MC1 isconstituted via the resistance change film 22 for each crossing portionof the local bit line 21 and the word line 23. The memory cells MC1 arearranged in a three-dimensional matrix along the X-direction, theY-direction, and the Z-direction.

A nonlinear resistance layer 26 is provided on the upper end 21 b of thelocal bit line 21. The resistance value of the nonlinear resistancelayer 26 depends on the applied voltage. The resistance value is lowerfor a higher voltage. The nonlinear resistance layer 26 is formed frome.g. tantalum silicon nitride (TaSiN) or titanium silicon nitride(TiSiN). A resistance change layer 27 is provided on the nonlinearresistance layer 26. The resistance change layer 27 is e.g. a CBRAMlayer in which e.g. a silicon oxide layer and a silver layer arestacked. The nonlinear resistance layer 26 and the resistance changelayer 27 form a resistance change film 28. As described later, theresistance change film 28 can assume three or more states different inresistance value.

A plurality of write word lines 29 extending in the Y-direction areprovided on the resistance change film 28. The plurality of write wordlines 29 are arranged periodically along the X-direction. Thus, thelocal bit lines 21 arranged along the Y-direction are commonly connectedto one write word line 29 via the respective resistance change films 28.The nonlinear resistance layer 26 and the resistance change layer 27 areconnected in series between the local bit line 21 and the write wordline 29. As a result, a memory cell MC2 is constituted via theresistance change film 28 for each crossing portion of the local bitline 21 and the write word line 29. The memory cells MC2 are arranged ina matrix along the X-direction and the Y-direction. In FIG. 1, part ofthe resistance change films 28 and part of the write word lines are notshown for clarity of illustration.

The memory device 1 further includes a control circuit 31. The controlcircuit 31 is placed e.g. around the region provided with the global bitline 11 in the silicon substrate (not shown), or between the siliconsubstrate and the global bit line 11.

Next, the operation of the memory device according to the embodiment isdescribed.

First, the operational principle of the memory device 1 according to theembodiment is briefly described.

The memory cell MC1 stores data in correspondence with a plurality ofresistance states of the resistance change film 22. The memory cell MC2assumes three or more states different in resistance value. Thus, thememory cell MC2 determines the magnitude of the maximum current, i.e.,compliance current, passed at write operation of the memory cell MC1.Difference in the magnitude of the compliance current passed at writeoperation of the memory cell MC1 results in different resistance statesof the memory cell MC1 after setting. Thus, the memory cell MC1 canassume a plurality of resistance states after setting. The plurality ofresistance states after setting and a resistance state before settingamount to three or more resistance states that can be assumed by thememory cell MC1. This enables multivalued memory.

In the following, the operation of each part is described in detail.

First, the behavior of the memory cell MC2 is described.

FIG. 3A is a timing chart showing the voltage applied to the resistancechange film. The horizontal axis represents time, and the vertical axisrepresents voltage. FIG. 3B is a graph showing the behavior of thememory cell MC2. The horizontal axis represents the voltage applied tothe resistance change film in the voltage application period. Thevertical axis represents the current flowing in the resistance changefilm in the current measurement period.

FIGS. 3A and 3B show a test example for characterizing the memory cellMC2. In the test example shown in FIGS. 3A and 3B, it is assumed that inthe initial state, the resistance change film 28 is in the highresistance state, i.e., the state of highest resistance value among thestates that can be assumed by the resistance change film 28. Forinstance, the resistance change layer 27 is a CBRAM layer made of asilicon oxide layer and a silver layer. In this case, this is a state inwhich no silver filament is formed in the silicon oxide layer.

From this state, as shown in FIG. 3A, in a voltage application periodt1, a write voltage is applied to the memory cell MC2 for a certaintime. This lowers the resistance value of the resistance change film 28.In the aforementioned example, silver atoms contained in the silverlayer are ionized and carried into the silicon oxide layer. The silverions are combined with electrons and precipitated in the silicon oxidelayer to form a fine filament of silver. Next, in a current measurementperiod t2, a certain read voltage Vread is applied to the memory cellMC2 to measure the value of current flowing in the memory cell MC2. Forinstance, the write voltage applied to the memory cell MC2 in thevoltage application period t1 is denoted by V1, and the current flowingin the current measurement period t2 is denoted by I1.

This cycle is repeated by sweeping the write voltage. That is, the writevoltage is increased step by step for each voltage application periodt1. For a higher write voltage, the resistance value of the resistancechange layer 27 is lower. In the aforementioned example, the silverfilament formed in the silicon oxide layer becomes thicker and morerobust. Furthermore, for a higher write voltage, the resistance value ofthe nonlinear resistance layer 26 is lower. Thus, of the voltage appliedto the entirety of the resistance change film 28, the voltage applied tothe nonlinear resistance layer 26 decreases. By this amount, the voltageapplied to the resistance change layer 27 increases. This further lowersthe resistance value of the resistance change layer 27. By such synergybetween the nonlinear resistance layer 26 and the resistance changelayer 27, for a higher write voltage, the resistance value of theresistance change film 28 is lower.

As a result, as shown in FIG. 3B, for different write voltages appliedin the voltage application period t1, the memory cell MC2 exhibitsdifferent read currents flowing in the current measurement period t2.For a higher write voltage, the read current is larger. That is,V1<V2<V3 results in I1<I2<I3. In other words, for a higher writevoltage, the resistance value of the memory cell MC2 is lower. Thus, theresistance value of the memory cell MC2 can be controlled by adjustingthe height of the write voltage.

Next, the behavior of the memory cell MC1 is described.

FIG. 4 is a graph showing the behavior of the memory cell MC1. Thehorizontal axis represents voltage, and the vertical axis representscurrent.

As shown in FIG. 4, the voltage applied to the memory cell MC1 in thehigh resistance state is continuously increased from zero. When thevoltage reaches the set voltage Vset, the resistance change film 22 isset. Thus, the memory cell MC1 is changed to a low resistance state.However, the state reached by the memory cell MC1 depends on themagnitude of the compliance current at the set time. For a largercompliance current, the resistance value of the memory cell MC1 islower. Thus, the magnitude of the current flowing upon application of aprescribed read voltage Vread to the memory cell MC1 also depends on themagnitude of the compliance current at the set time.

In the example shown in FIG. 4, the magnitude of the compliance currentassumes three levels of Icomp1, Icomp2, and Icomp3. The read currents ofthe memory cell MC1 after being set by these compliance currents areIread1, Iread2, and Iread3, respectively. In the case of performing noset operation, i.e., when the memory cell MC1 is in the high resistancestate, the read current flowing upon application of the read voltageVread is Iread0. Thus, the read currents of the memory cell MC1 canassume four levels in total. Data of 2 bits can be stored by assigningvalues “00”, “01”, “10”, and “11” to these levels.

Next, the overall operation of the memory device 1 according to theembodiment is described specifically.

FIG. 5 is a timing chart showing the operation of the memory deviceaccording to the embodiment. The horizontal axis represents time, andthe vertical axis represents the potential applied to each interconnect.

It is assumed that in the initial state, the memory cell MC1 and thememory cell MC2 are both in the high resistance state.

As shown in step S1 of FIG. 5, first, a memory cell MC1 to be written isselected. The memory cell MC2 connected to the memory cell MC1 thusselected is turned to low resistance.

Specifically, the control circuit 31 applies a set potential V_(set2) ofthe memory cell MC2 to the selected write word line 29, and applies apotential of V_(set2)/2 equal to half the set potential V_(set2) to thenon-selected write word line 29. Furthermore, the control circuit 31applies 0 V to both the selected word line 23 and the non-selected wordline 23, or places them in the floating state. The control circuit 31applies an on-potential V_(SG) to the selected gate electrode 16. Thecontrol circuit 31 applies 0 V to the non-selected gate electrode 16, orplaces it in the floating state. The control circuit 31 applies 0 V tothe selected global bit line 11, and applies a potential of V_(set2)/2to the non-selected global bit line 11.

Thus, the selected TFT 19 turns to the conducting state. The selectedlocal bit line 21 is applied through the TFT 19 with a potential of 0 Vapplied to the selected global bit line 11. On the other hand, theselected write word line 29 is applied with the set potential V_(set2)of the memory cell MC2. Thus, the selected memory cell MC2 is appliedwith a voltage of V_(set2)−0. As a result, the memory cell MC2 is setand turns to the low resistance state. However, as described above, thelow resistance state of the memory cell MC2 has a plurality of levels.The memory cell MC2 assumes one of these levels. In other words, theresistance change film 28 turns to a state except the state of highestresistance value among the three or more possible states. On the otherhand, the non-selected memory cell MC2 is applied with a potential ofV_(set2)/2 on both sides, or placed in the floating state on the localbit line 21 side. Thus, the non-selected memory cell MC2 is not set.

Next, as shown in step S2 of FIG. 5, read operation is performed on thememory cell MC2 to verify whether it is placed in an appropriate state.

Specifically, the control circuit 31 applies a read potential V_(read2)of the memory cell MC2 to the selected write word line 29, and applies apotential of V_(read2)/2 equal to half the read potential V_(read2) tothe non-selected write word line 29. Furthermore, the control circuit 31applies 0 V to both the selected word line 23 and the non-selected wordline 23, or places them in the floating state. The control circuit 31applies the on-potential V_(SG) to the selected gate electrode 16. Thecontrol circuit 31 applies 0 V to the non-selected gate electrode 16, orplaces it in the floating state. The control circuit 31 applies 0 V tothe selected global bit line 11, and applies a potential of V_(read2)/2to the non-selected global bit line 11.

Thus, the selected local bit line 21 is applied with 0 V from theselected global bit line 11 through the TFT 19 placed in the conductingstate. Furthermore, the selected write word line 29 is applied with theread potential V_(read2) of the memory cell MC2. Thus, the selectedmemory cell MC2 is applied with a voltage of V_(read2)−0. As a result, acurrent flows in the path made of the write word line 29, the memorycell MC2, the local bit line 21, the silicon member 12, and the globalbit line 11. The magnitude of this current is measured by a senseamplifier of the control circuit 31. Thus, the resistance state of thememory cell MC2 can be verified.

The aforementioned steps S1 and S2 may be repeated until the memory cellMC2 turns to a prescribed resistance state.

Next, as shown in step S3 of FIG. 5, data is written to the selectedmemory cell MC1. At this time, the memory cell MC2 has been placed in aprescribed resistance state except the state of highest resistancevalue.

Specifically, the control circuit 31 applies a set potential V_(set1) ofthe memory cell MC1 to the selected write word line 29, and applies apotential of V_(set1)/2 equal to half the set potential V_(set1) to thenon-selected write word line 29. Furthermore, the control circuit 31applies 0 V to the selected word line 23, and applies a potential ofV_(set1)/2 to the non-selected word line 23. The control circuit 31applies 0 V to all the gate electrodes 16 and all the global bit lines11, or places them in the floating state.

Thus, all the TFTs 19 turn to the non-conducting state. The local bitline 21 is applied with the set potential V_(set1) from the selectedwrite word line 29 through the memory cell MC2. The selected word line23 is applied with 0 V. Thus, the selected memory cell MC1 is appliedwith a voltage of V_(set1)−0. As a result, the selected memory cell MC1is set and turns to the low resistance state. The moment the memory cellMC1 is set, a large current flows in the path made of the write wordline 29, the memory cell MC2, the local bit line 21, the memory cellMC1, and the word line 23. However, the maximum of the current flowingat this time, i.e., compliance current, is determined by the resistancestate of the memory cell MC2. The resistance state of the memory cellMC1 after setting depends on the magnitude of the compliance current.Thus, the resistance state of the selected memory cell MC1 is alsodetermined by the resistance state of the memory cell MC2. On the otherhand, the non-selected memory cell MC1 is applied with a voltage ofV_(set1)/2 or 0 V. Thus, the non-selected memory cell MC1 is not set.Accordingly, data is written to the selected memory cell MC1.

Next, as shown in step S4 of FIG. 5, the memory cell MC2 is turned tohigh resistance.

Specifically, the control circuit 31 applies 0 V to the selected writeword line 29, and applies a potential of V_(reset2)/2 equal to half areset potential V_(reset2) to the non-selected write word line 29.Furthermore, the control circuit 31 applies 0 V to all the word lines23, or places them in the floating state. The control circuit 31 appliesthe on-potential V_(SG) to the selected gate electrode 16. The controlcircuit 31 applies 0 V to the non-selected gate electrode 16, or placesit in the floating state. The control circuit 31 applies the resetpotential V_(reset2) to the selected global bit line 11, and applies apotential of V_(set2)/2 to the non-selected global bit line 11.

Thus, the selected TFT 19 turns to the conducting state. The selectedlocal bit line 21 is applied through the TFT 19 with the reset potentialV_(reset2) applied to the selected global bit line 11. On the otherhand, the selected write word line 29 is applied with 0 V. Thus, theselected memory cell MC2 is applied with a voltage of V_(reset2)−0. As aresult, the memory cell MC2 is reset and turns to the high resistancestate, i.e., the state of highest resistance value among the possiblestates. On the other hand, the non-selected memory cell MC2 is appliedwith a potential of V_(reset2)/2 on both sides, or placed in thefloating state on the local bit line 21 side. Thus, the non-selectedmemory cell MC2 is not reset. At the time of read operation and eraseoperation of the memory cell MC1 described below, the memory cell MC2 isalways placed in the high resistance state.

Next, as shown in step S5 of FIG. 5, data is read from the memory cellMC1.

Specifically, the control circuit 31 applies 0 V to all the write wordlines 29, or places them in the floating state. The control circuit 31applies 0 V to the selected word line 23, and applies a potential ofV_(read1)/2 equal to half a read potential V_(read1) to the non-selectedword line 23. The control circuit 31 applies the on-potential V_(SG) tothe selected gate electrode 16. The control circuit 31 applies 0 V tothe non-selected gate electrode 16, or places it in the floating state.The control circuit 31 applies the read potential V_(read1) to theselected global bit line 11, and applies a potential of V_(read1)/2 tothe non-selected global bit line 11.

Thus, the selected local bit line 21 is applied with the read potentialV_(read1) applied to the selected global bit line 11 through the TFT 19placed in the conducting state. Furthermore, the selected word line 23is applied with 0 V. Thus, the selected memory cell MC1 is applied witha voltage of V_(read1)−0. As a result, a current flows in the path madeof the word line 23, the memory cell MC1, the local bit line 21, thesilicon member 12, and the global bit line 11. The magnitude of thiscurrent is measured by the sense amplifier of the control circuit 31.Thus, the resistance state of the memory cell MC1 can be evaluated, andthe value stored in the memory cell MC1 can be read. On the other hand,the non-selected memory cell MC1 is applied with a potential ofV_(read1)/2 on both sides, or placed in the floating state on the localbit line 21 side. Thus, no substantial current flows therein. At thistime, all the memory cells MC2 are placed in the high resistance state,and all the write word lines 29 are placed at 0 V or in the floatingstate. Thus, no substantial current flows from the local bit line 21 tothe write word line 29.

Next, as shown in step S6 of FIG. 5, data is erased from the memory cellMC1.

Specifically, the control circuit 31 applies 0 V to all the write wordlines 29, or places them in the floating state. The control circuit 31applies a reset potential V_(reset1) of the memory cell MC1 to theselected word line 23, and applies a potential of V_(reset1)/2 equal tohalf the reset potential V_(reset1) to the non-selected word line 23.The control circuit 31 applies the on-potential V_(SG) to the selectedgate electrode 16. The control circuit 31 applies 0 V to thenon-selected gate electrode 16, or places it in the floating state. Thecontrol circuit 31 applies 0 V to the selected global bit line 11, andapplies a potential of V_(reset1)/2 to the non-selected global bit line11.

Thus, the selected local bit line 21 is applied with 0 V from theselected global bit line 11 through the TFT 19 placed in the conductingstate. Furthermore, the selected word line 23 is applied with the resetpotential V_(reset1). Thus, the selected memory cell MC1 is applied witha voltage equal to the reset potential V_(reset1)−0. As a result, theselected memory cell MC1 is reset and turns to the high resistancestate. On the other hand, the non-selected memory cell MC1 is appliedwith a voltage of V_(reset1)/2 or 0 V. Thus, the non-selected memorycell MC1 is not reset. Accordingly, data is erased from the selectedmemory cell MC1. Also at this time, all the memory cells MC2 are placedin the high resistance state, and all the write word lines 29 are placedat 0 V or in the floating state. Thus, no substantial current flows fromthe local bit line 21 to the write word line 29.

Next, the effect of the embodiment is described.

In the memory device 1 according to the embodiment, the write word line29 is provided and connected to the local bit line 21 through the memorycell MC2. Thus, by controlling the resistance state of the memory cellMC2, the magnitude of the compliance current at the time of setting thememory cell MC1 can be selected to select the resistance value after thememory cell MC1 is set. As a result, multivalued data can be stored inthe memory cell MC1. Thus, the memory device 1 has high memory density.

The resistance change film 28 constituting the memory cell MC2 isprovided above the local bit line 21. Thus, provision of the resistancechange film 28 does not lengthen the arrangement pitch of the local bitlines 21 in the X-direction and the Y-direction. Accordingly,miniaturization of the memory device 1 is not hampered.

The embodiment described above can realize a memory device having highmemory density and a method for driving the same.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the invention.

What is claimed is:
 1. A memory device comprising: a first interconnectextending in a first direction; a second interconnect extending in asecond direction crossing the first direction; a third interconnectextending in a third direction crossing a plane including the firstdirection and the second direction; a fourth interconnect extending inthe third direction; a semiconductor member connected between a firstend of the second interconnect and the first interconnect; a firstresistance change film connected between a side surface of the secondinterconnect and the third interconnect; and a second resistance changefilm connected between a second end of the second interconnect and thefourth interconnect.
 2. The device according to claim 1, wherein thefirst end and the second end are both ends in the second direction ofthe second interconnect, and the side surface is a surface facing thefirst direction of the second interconnect.
 3. The device according toclaim 1, further comprising: an electrode placed on the first directionside of the semiconductor member and extending in the third direction.4. The device according to claim 1, wherein the second resistance changefilm includes: a nonlinear resistance layer having a resistance valuedepending on voltage; and a resistance change layer, and the nonlinearresistance layer and the resistance change layer are connected in seriesbetween the second interconnect and the fourth interconnect.
 5. Thedevice according to claim 4, wherein the nonlinear resistance layercontains silicon, nitrogen, and at least one of tantalum and titanium.6. The device according to claim 1, wherein the second resistance changefilm can assume three or more states different in resistance value. 7.The device according to claim 6, further comprising: a control circuit,wherein the control circuit brings the semiconductor member intoconduction and applies a first voltage, a second voltage of oppositepolarity to the first voltage, or a third voltage having the samepolarity as the second voltage and having a larger absolute value thanthe second voltage between the first interconnect and the fourthinterconnect.
 8. The device according to claim 7, wherein the controlcircuit changes a resistance value of the first resistance change filminto a value corresponding to the second voltage by applying a voltagebetween the fourth interconnect and the third interconnect, afterapplying the second voltage between the first interconnect and thefourth interconnect, and the control circuit changes a resistance valueof the first resistance change film into a value corresponding to thethird voltage by applying a voltage between the fourth interconnect andthe third interconnect, after applying the third voltage between thefirst interconnect and the fourth interconnect.
 9. The device accordingto claim 7, wherein the control circuit brings the semiconductor memberinto conduction and applies a voltage between the first interconnect andthe third interconnect after applying the first voltage between thefirst interconnect and the fourth interconnect while data is read. 10.The device according to claim 7, wherein the control circuit turns thefirst resistance change film to a state of highest resistance value bybringing the semiconductor member into conduction and applying a voltagebetween the first interconnect and the third interconnect after applyingthe first voltage between the first interconnect and the fourthinterconnect.
 11. The device according to claim 7, wherein the controlcircuit changes a resistance value of the first resistance change filminto a value corresponding to the second voltage by applying a voltagebetween the fourth interconnect and the third interconnect, afterbringing the semiconductor member into conduction and applying thesecond voltage between the first interconnect and the fourthinterconnect, or the control circuit changes a resistance value of thefirst resistance change film into a value corresponding to the thirdvoltage by applying a voltage between the fourth interconnect and thethird interconnect, after bringing the semiconductor member intoconduction and applying the third voltage between the first interconnectand the fourth interconnect, then the control circuit brings thesemiconductor member into conduction and applies the first voltagebetween the first interconnect and the fourth interconnect.
 12. A memorydevice comprising: a first interconnect extending in a first direction;a second interconnect extending in a second direction crossing the firstdirection; a third interconnect extending in a third direction crossinga plane including the first direction and the second direction; a firstresistance change film connected between the first interconnect and thesecond interconnect; a second resistance change film connected betweenthe first interconnect and the third interconnect and being capable ofassuming three or more states different in resistance value; and acontrol circuit, the control circuit being configured to turn the secondresistance change film to a state except the state of highest resistancevalue among the three or more states by applying a voltage between thefirst interconnect and the third interconnect, the control circuit beingconfigured to change a resistance value of the first resistance changefilm by applying a potential to the first interconnect from the thirdinterconnect through the second resistance change film and applying apotential to the second interconnect, and the control circuit beingconfigured to turn the second resistance change film to the state ofhighest resistance value among the three or more states by applying avoltage between the first interconnect and the third interconnect. 13.The device according to claim 12, wherein the control circuit measures acurrent flowing in the first resistance change film by applying avoltage between the first interconnect and the second interconnect whenthe second resistance change film is in the state of highest resistancevalue among the three or more states.
 14. The device according to claim12, wherein the control circuit turns the first resistance change filmto a state of highest resistance value by applying a voltage between thefirst interconnect and the second interconnect when the secondresistance change film is in the state of highest resistance value amongthe three or more states.
 15. The device according to claim 12, furthercomprising: a fourth interconnect extending in the third direction; anda semiconductor member connected between the first interconnect and thefourth interconnect, wherein the control circuit applies a potentialfrom the fourth interconnect through the semiconductor member to thefirst interconnect by bringing the semiconductor member into conductionand applying a potential to the fourth interconnect.
 16. The deviceaccording to claim 12, wherein the second resistance change filmincludes: a nonlinear resistance layer having a resistance valuedepending on voltage; and a resistance change layer, and the nonlinearresistance layer and the resistance change layer are connected in seriesbetween the first interconnect and the third interconnect.
 17. Thedevice according to claim 16, wherein the nonlinear resistance layercontains silicon, nitrogen, and at least one of tantalum and titanium.18. A method for driving a memory device including a first interconnectextending in a first direction, a second interconnect extending in asecond direction crossing the first direction, a third interconnectextending in a third direction crossing a plane including the firstdirection and the second direction, a first resistance change filmconnected between the first interconnect and the second interconnect,and a second resistance change film connected between the firstinterconnect and the third interconnect and being capable of assumingthree or more states different in resistance value, the methodcomprising: turning the second resistance change film to a state exceptthe state of highest resistance value among the three or more states byapplying a voltage between the first interconnect and the thirdinterconnect; changing a resistance value of the first resistance changefilm by applying a potential to the first interconnect from the thirdinterconnect through the second resistance change film and applying apotential to the second interconnect; and turning the second resistancechange film to the state of highest resistance value among the three ormore states by applying a voltage between the first interconnect and thethird interconnect.
 19. The method according to claim 18, furthercomprising: measuring a current flowing in the first resistance changefilm by applying a voltage between the first interconnect and the secondinterconnect when the second resistance change film is in the state ofhighest resistance value among the three or more states.
 20. The methodaccording to claim 18, further comprising: turning the first resistancechange film to a state of highest resistance value by applying a voltagebetween the first interconnect and the second interconnect when thesecond resistance change film is in the state of highest resistancevalue among the three or more states.